An insulated-gate field-effect transistor ("IGFET") is a semiconductor device in which a gate dielectric layer electrically insulates a channel region of a semiconductor body from an overlying gate electrode. The channel region extends between a source zone and a drain zone that adjoin a body region of the semiconductor body, the body region (often referred to as the substrate region or the substrate) being of opposite conductivity type to the source and drain. Charge carriers--i.e., electrons for an n-channel IGFET and holes for a p-channel IGFET--move from the source through the channel region to the drain when appropriate voltages are applied to the gate electrode, source, and body region. By suitably controlling these voltages, the IGFET switches between an on condition and an off condition.
IGFETs can be placed in two general categories according to their conducting characteristics: normally off, sometimes referred to as enhancement mode, and normally on, sometimes referred to as depletion mode. The terms "normally off" and "normally on" are applied to an IGFET with regard to the transistor's condition when the gate-to-source voltage is zero and the source is connected to the body region--i.e., the gate electrode, source, and body region are at the same voltage, such as ground reference. In a normally off IGFET with zero gate-to-source voltage, substantially no charge carriers flow from the source to the drain. Depending on whether the IGFET is an n-channel or p-channel device, the gate-to-source voltage must either be raised above a positive threshold voltage or dropped below a negative threshold voltage for the transistor to be turned on.
A normally on IGFET operates in substantially the opposite way to a normally off IGFET. Charge carriers flow from the source to the drain in a normally on IGFET at zero gate-to-source voltage. Depending on whether the normally on IGFET is an n-channel or p-channel device, the gate-to-source voltage must either be dropped below a negative threshold voltage or raised above a positive threshold voltage for the transistor to be turned off.
The channel region in an IGFET may be of the same conductivity type as, or of opposite conductivity type to, the source and drain.
When the channel region is of opposite conductivity type to the source and drain, the channel region is of the same conductivity type as the body region and, although typically doped to a different level than the bulk of the body region, merges junctionlessly into the bulk of the body region. An IGFET whose channel region is of opposite conductivity type to the source and drain usually is a normally off device since no conduction path from the source to the drain extends through the channel region at zero gate-to-source voltage. By applying a gate-to-source voltage suitable to place the IGFET in a conductive condition, charge carriers are attracted to the upper surface of the channel region and cause inversion to occur in a thin surface layer of the channel region. The inverted surface layer forms a conductive surface channel extending from the source to the drain. As a result, this type of IGFET is commonly referred to as a "surface-channel" device.
When the channel region is of the same conductivity type as the source and drain, the channel region is of opposite conductivity type to the body region and forms a channel/body pn junction with the body region. An IGFET having a channel region of the same conductivity type as the source and drain may be a normally on device or a normally off device dependent, among other things, on the doping level in the channel region. If the net doping level in the channel region is sufficiently high, the transistor is a normally on device. If the net channel doping, although of the same conductivity type as the source/drain doping, is sufficiently low, a depletion (or space charge) region extends across the full vertical thickness of the channel region when the gate electrode, source, and body region are at the same voltage. The transistor is then a normally off device.
In a normally off IGFET whose channel region is of the same conductivity type as the source and drain, current conduction from the source to the drain can occur along a surface layer of the channel region or through a subsurface layer of the channel region. Whether conduction occurs by way of a surface channel, or a subsurface channel, depends on various factors such as the doping level of the channel region, the doping level of the body region, and the characteristics of the gate structure.
Consider a normally off IGFET whose channel region is of the same conductivity type as the source and drain and whose gate electrode consists of polycrystalline silicon ("polysilicon") doped to be of the same conductivity type as the body region. If the net dopant concentration in the channel region in such a device is less than a predetermined value dependent on the net dopant concentration in the bulk of the body region, application of a gate-to-source voltage sufficient to make the transistor conductive typically causes a conductive surface channel to form in the otherwise charge-depleted channel region. Conversely, if the net dopant concentration in the channel region is greater than the predetermined value, application of a gate-to-source voltage sufficient to make the transistor conductive typically causes the depletion region to split into a pair of vertically separated depletion regions. The zone between the two depletion regions forms a subsurface channel, commonly termed a buried channel.
An IGFET having a channel region of the same conductivity type as the source and drain is variously referred to by persons working in the semiconductor art by anyone of the following terms: buried channel MOSFET, implanted-channel MOSFET, and junction MOSFET. Unfortunately, all of these terms are unsatisfactory. For example, characterizing such a transistor as a "buried channel MOSFET" is misdescriptive because source-to-drain conduction can occur through either a surface channel or a buried channel depending on the doping of the channel region relative to the doping of the body region. As to "implanted-channel MOSFET", the channel region is normally created by ion implantation but does not have to be ion implanted. The term "junction MOSFET" does not make it clear that the "junction" is the channel/body junction. Consequently, "junction MOSFET" is confusingly similar to the term "junction field-effect transistor" applied to a field-effect transistor having no gate dielectric layer.
Herein, an IGFET whose channel region is of the same conductivity type as the source and drain is generally referred to as a "channel-junction insulated-gate field-effect transistor," where the modifier "channel-junction" refers to the pn junction formed between the channel region and the body region. Consequently, a channel-junction insulated-gate field-effect transistor ("CJIGFET") generally means any transistor commonly referred to as a buried-channel MOSFET, an implanted-channel MOSFET, or a junction MOSFET. In particular, a normally off CJIGFET is a normally off IGFET having a channel region of the same conductivity type as the source and drain.
CJIGFETs are often used in complementary-IGFET applications in which one of the two types of opposite-polarity transistors is a CJIGFET while the other type of transistor is a surface-channel IGFET--i.e., a device whose channel region is of opposite conductivity type to the source and drain. As an example of such a "CMOS" application, see Hu et al, "Design and Fabrication of p-channel FET for 1-.mu.m CMOS Technology," IEDM Tech. Dig., 1982, pages 710-713. In Hu et al, the p-channel device is a CJIGFET while the n-channel device is a surface-channel IGFET. The opposite occurs in Parillo et al, "A Fine-Line CMOS Technology That Uses P+ Polysilicon/Silicide Gates for NMOS and PMOS Devices," IEDM Tech. Dig., 1984, pages 418-422.
In general, CJIGFETs can be integrated relatively easily into CMOS process flows. Accordingly, CJIGFETs are attractive for use in products such as CMOS memories and CMOS microprocessors fabricated in large volumes. Also, CJIGFETs avoid the high gate electric field and bulk charge that cause deleterious effects in surface-channel IGFETs.
In a polysilicon-gate IGFET, the type of doping in the polysilicon of the gate electrode has a large influence on the threshold voltage. Normally, the polysilicon gate material is heavily doped to achieve a low resistivity. The Fermi energy level of heavily doped n-type polysilicon is close to the energy at the edge of the conduction band of silicon, while the Fermi energy level of heavily doped p-type polysilicon is close to the energy at the edge of the valance band of silicon.
The work function of a material is the difference between the vacuum energy level and the Fermi energy level of the material. Inasmuch as the silicon conduction band energy is approximately 1.1 eV greater than the silicon valance band energy, the work function of heavily doped p-type polysilicon is typically about 1.1 eV greater than the work function of heavily doped n-type polysilicon. This translates into an approximate 1.1-V effect on the threshold voltage. That is, changing the gate material from heavily doped p-type polysilicon to heavily doped n-type polysilicon causes the threshold voltage of a polysilicon-gate IGFET to be reduced by approximately 1.1 V, and vice versa.
Field-effect transistors used in integrated circuits are progressively being made smaller and smaller. As device miniaturization continues, the circuit supply voltages become progressively smaller. Accordingly, it is necessary for the magnitude of the threshold voltage to be decreased correspondingly. Also, in a complementary-IGFET application, it is desirable that the p-channel threshold voltage be of approximately the same magnitude as the n-channel threshold voltage.
Hillenius et al, "Gate Material Work Function Considerations For 0.5 .mu.m CMOS," Procs. Intl. Conf. Computer Design, 1985, pages 147-150, addresses the preceding issues. Hillenius et al discusses various CMOS architectures in which the threshold voltages of both the n-channel and p-channel devices have approximately equal magnitudes in the vicinity of 0.5 V. Among these architectures are arrangements in which one of the types of complementary IGFETs is a CJIGFET while the other is a surface-channel IGFET. Although concluding that a doped polysilicon gate electrode is the best for complementary IGFETs of 0.5-.mu.m gate length, Hillenius et al suggests that p-channel and n-channel threshold voltages of approximately equal magnitude could be achieved by using tungsten for the gate electrodes of both types of IGFETs. The reason for this is that the work function of tungsten places the Fermi energy level near the "midgap" of silicon--i.e., approximately half way between the energy levels at the conduction and valence bands of silicon.
King et al, "A Polycrystalline-Si.sub.1-x Ge.sub.x, Gate CMOS Technology," IEDM Tech. Dig., 1990, pages 253-256, discusses various CMOS architectures directed towards a 0.7-V magnitude for the threshold voltages of both the n-channel and p-channel devices. At least one of the two types of complementary IGFETs in each of the CMOS cases considered in King et al is a surface-channel IGFET. King proposes that heavily doped p-type polycrystalline silicon-germanium material be used for the gate electrode of both the n-channel and p-channel transistors. When the heavily doped p-type polycrystalline silicon-germanium material is 60% germanium, King reports that the work function is reduced by 0.3 V compared to that of p-type silicon. This brings the Fermi energy level of the silicon-germanium material close to the midgap of silicon.
Hillenius et al and King et al offer significant advantages. However, each of their complementary-IGFET architectures includes at least one surface-channel IGFET. Consequently, all of the complementary transistor architectures in Hillenius et al and King et al are subject to the high gate electric field and bulk charge problems that generally arise with surface-channel IGFETs.
Vinal, U.S. Pat. No. 4,990,974, describes a CJIGFET whose threshold voltage is twice the "Fermi" potential. This IGFET, referred to by Vinal as a Fermi-FET, is a silicon device having a silicon oxide gate dielectric and a doped polysilicon gate electrode of opposite conductivity type to the source and drain. Advantageously, Vinal reports that the value of the threshold voltage is independent of the gate oxide thickness, channel length, drain voltage, and substrate doping. To attain these benefits, the net average channel dopant concentration is set equal to the bulk substrate dopant concentration. Also, the net dopant concentration in the polysilicon gate electrode must equal the bulk substrate dopant concentration.
The capability reported by Vinal to make the threshold voltage insensitive to gate oxide thickness, channel length, and drain voltage is highly advantageous. However, the parameter design space in which Vinal can achieve these advantages is very small. This presents severe fabrication difficulties. In addition, the magnitude of the two-Fermi threshold voltage is typically in the vicinity of 0.7 V for a silicon CJIGFET. While this is moderately low, many future applications will require a threshold voltage magnitude of 0.5 V or less, a level unattainable with Vinal's Fermi-FET.
Vinal discloses that his Fermi-FET design can be used in complementary-FET applications. In that event, the n-channel Fermi-FET has a p-doped polysilicon gate electrode while the p-channel Fermi-FET has an n-doped polysilicon gate electrode. The necessity to dope the gate electrodes with dopants of opposite conductivity type increases the transistor fabrication difficulty, especially as gate electrodes are made shorter and enter the sub-.mu.m range of minimum feature size.
For low supply voltage applications, it would be desirable to have a complementary-IGFET architecture in which the threshold voltages of both the n-channel and p-channel transistors can readily be set at approximately equal magnitudes of 0.5 V or less and do not vary significantly with parameters such as the gate dielectric thickness and details of the channel doping profile. This is particularly important in IC fabrication process developed for analog and mixed signal applications where the transistor modeling from die to die and wafer to wafer is critical. It would also be desirable to have a substantial design space so as to enable practical device fabrication. Furthermore, it would be desirable to form the gate electrodes from substantially the same physical material so as to simply transistor fabrication.